The present invention relates to apparatus and processes useful in multiple processor computer systems. More particularly, the present invention is concerned with methods and apparatus for controlling and/or accommodating the time delay associated with passage of a signal in the form of an electrical and/or optical pulse through a discrete component. Still further, the present invention accepts master clock pulses from a source and distributes a multiplicity of replications of the master clock pulses so as to allow distribution of those pulses throughout a complex system in a carefully controlled manner. This invention relates to devices and methods which assist in ensuring that timing pulses originating from a master clock pulse source are distributed for controlling a variety of electronic data handling and/or computer functions so as to arrive at a plurality of distribution points within an extremely close time tolerance and with well preserved signal integrity as compared to the master clock pulses.